Semiconductor USA

Samsung Austin R&D Center (SARC) &
San Jose Advanced Computing Lab (ACL)

Creating High-performance, Low-power CPU & GPU Architectures and Designs


The Samsung Austin R&D Center (SARC) was founded in 2010 to develop high-performance, low-power, complex CPU and System IP (Coherent Interconnect and memory controller) architectures and designs for Samsung’s System LSI division. The San Jose Advanced Computing Lab (ACL) was opened in 2017 and GPU IP (leveraging 5 years initial development from another division) was added to the joint charter. The engineering team has extensive experience and a broad background in the development of advanced CPU & GPU designs and System IP for various market segments. The management team has extensive experience building world-class teams, fostering an outstanding work environment and enabling creativity.

Our mission is to develop the best CPU, GPU and System IP for System LSI products. This requires a highly competitive feature set and excellent overall performance with very low power consumption.

Current focus areas include:

  • Performance and Power Architecture
  • System simulation and applied data science methods and tools
  • Performance modeling and analysis
  • Workload analysis and characterization
  • Compiler and system software optimization
  • Power and thermal characterization, modeling, and analysis
  • GPU Driver Development
  • CPU, GPU and System IP (Coherent Interconnect and Memory Controllers) Development
  • Architecture
  • Micro-architecture
  • RTL
  • CPU, GPU and System IP Verification
  • Functional and formal verification at all levels of abstraction
  • Physical Implementation
  • Fast RTL to GDS with the best PPA (high-performance, low-power, and within a small area)
  • Technology analysis and custom circuit development
  • Test chip development for technology validation
  • Custom circuits for high-end CPUs
  • Design Methodology
  • Development of Power, Performance and Area (PPA) enhancing tools
  • Support for design infrastructure
  • Post-Silicon Validation