Location: San Jose, California
Job Category: Internship
Samsung Semiconductor’s New Memory Technology (NMT) Lab, located in San Jose, CA has teams of leading scientists and engineers developing advanced materials and devices that will enable future STT-MRAM* memory technology to achieve widespread commercial adoption. The lab is developing embedded and standalone memories as well as exploring potential uses of spintronics technology in logic devices. The lab’s industry-leading teams of researchers have strong technical background in physics, material science, and electrical engineering. The lab is pioneering ground-breaking R&D on STT-MRAM technology. Unlike traditional semiconductor technology, lab researchers are exploring technologies that harness the spin of an electron and its interaction with engineered magnetic materials – the essence of spintronics – as a potential basis for future memory technology. STT-MRAM is a scalable, next -generation, semiconductor memory technology that is nonvolatile and fast, operating at low power with unlimited endurance. Scientists and engineers at the NMT Lab work on internal advanced R&D projects in material and process development, modeling and simulation, and design and characterization. They do so in collaboration with leading industrial research groups and top university researchers around the globe.
The Test Development for STT-MRAM Intern will work as part of a team of talented NMT engineers on improving software and hardware for STT-MRAM testing. She or he will experience a wide range of engineering problems ranging from test design, experimental matrix definition, and data analysis.