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Sr Staff ASIC Engineer – DFT Design Chip Lead

Location: San Jose, California
Job Category: Engineering - Hardware

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Job Title: Sr Staff ASIC Engineer – DFT Design Chip Lead


High performance computing and networking have been going through rapid transformation due to the explosive growth in cloud datacenter and automotive electronics. This growth has been driving increasing needs for innovative and integrated SoC Design services and solutions. Samsung Foundry is expanding SoC Design Engineering to support this need in North America.

Job Responsibilities:

This position will be responsible for hierarchical full chip DFT (Design for Test) features that support ATE, in system test, debug and diagnostic needs of the design. You will be responsible for DFT Insertion, writing DFT timing constraints, generating, verifying and debugging test vectors. This role includes post silicon validation, validating and debugging test vectors on ATE during silicon bring-up as well as test bench generation & simulation and Samsung DFT insertion methodology support for customers

The successful candidate is expected to have:

  • Solid experience in DFT and Test insertion, especially big die implementation
  • Solid experience in JTAG protocols, Scan, and BIST architectures like memory BIST, IO BIST, LBIST
  • Solid knowledge of NOC (Network on Chip from Netspeed / Arteris)
  • Solid experience in post silicon validation, validating and debugging test vectors on ATE during silicon bring-up.
  • Solid experience in writing DFT timing constraints
  • Solid experience of working closely with STA and PD engineers to close timing in test mode
  • Solid experience in generating, verifying and debugging test vectors
  • Excellent communication skills
  • Ability to work independently and mentor junior team members
  • Working with customers

Required Skills:

  • BS or BE minimum with at least 10 years of additional industry experience.
  • Direct experience in DFT insertion in ASIC or SoC design, with significant hands on experience in large complex projects.
  • Strong knowledge in Test bench generation & simulation in SoC / CPU / GPU Designs.
  • Comfortable working with and managing 3rd party teams.
  • Scripting languages (Tcl, Perl, Python), Documents Word processing, Power Points), Spreadsheet, email;
  • Highly passionate and energetic.
  • Frequent customer and partner visits. Domestic and international travel.

Preferred Skills:

  • MS/PhD preferred.
  • Experience working on complex designs with NOC (Network on chip) from Netspeed or Arteris


Samsung Semiconductor Inc (SSI), an equal opportunity employer, is a world leader in Memory, System LSI, and LCD technologies. Headquartered in San Jose, California, SSI is a wholly-owned U.S. subsidiary of Samsung Electronics Co., Ltd.- the second largest semiconductor manufacturer in the world and the industry's volume and technology leader in DRAM, NAND Flash, SSDs, mobile DRAM and graphics memory. It is one of the largest providers of system logic, imaging and LED lighting solutions, as well as providing advanced process design and manufacturing for fabless companies. Samsung Semiconductor, Inc. also has a research and innovation center with numerous labs providing product design and research in: logic, memory, image sensors, displays and mobile technologies. In addition, the company supports Samsung Display Company, the largest producer of LCD and OLED displays.


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